The process of manufacturing semiconductor integrated circuit devices mainly comprises a wafer fabrication sub-process for forming semiconductor integrated circuit devices in a grid pattern on a wafer and an assembly sub-process for cutting or dicing the wafer into individual semiconductor integrated circuit devices then packaging. In the last step of the wafer fabrication sub-process, the electric characteristics of each semiconductor integrated circuit device are inspected to determine whether it is defective. Such inspection called probing.
Referring to FIGS. 16 to 20, examples of prior art will be described.
FIG. 16 shows an arrangement of semiconductor integrated circuit devices on a wafer. In general, each semiconductor integrated circuit device is rectangular, and several thousands of semiconductor integrated circuit devices 1 are formed in a grid pattern on a wafer 10.
To perform the probing, it is necessary to connect electrically an IC tester to each semiconductor integrated circuit device 1. The probing is generally carried out by attaching the tips of probe needles 8 (cantilevered tungsten needles, etc.) to a probe card into mechanical contact with the bonding pads 9 of each semiconductor integrated circuit device 1. The probing of a wafer is finished by shifting the probe card to the next semiconductor integrated circuit device 1, and repeating the same step several thousands times.
Shown in FIG. 17 are the tips of probes put into contact with the bonding pads of a semiconductor integrated circuit device 1 and shown in FIG. 18 is wire bonding. The semiconductor integrated circuit device 1 shown in FIG. 17 has an internal logic area 5 in its central area, an input and output buffer area 3 around the internal logic area 5, and a pad area 2 around the input and output buffer area 3.
Input and output buffers 4 are arranged in the input and output buffer area 3 and bonding pads 9 (six bonding pads, each indicated by an empty box, are arranged along each side in FIG. 17) are arranged in the pad area 2.
If the bonding pads 9 are arranged along the four sides of a semiconductor integrated circuit device 1, a probe card with probe needles 8 are arranged so that the probe needles 8 are positioned along the four sides of the semiconductor integrated circuit device 1, as shown in FIG. 17.
If bonding pads 9 are arranged along the four sides of a semiconductor integrated circuit device 1, the lead frame of the package is disposed outside the bonding pads 9, along the four sides of the semiconductor integrated circuit device 1, to connect each bonding pad 9 to an inner lead 7 with a bonding wire 6 as shown in FIG. 18. Namely, because the bonding pads 9 are arranged along the four sides of the semiconductor integrated circuit device 1, the inner leads 7 are arranged along the four sides of the package to simply the connections between the bonding pads 9 to the inner leads 7.
One typical example of the wire bonding is the above connection of bonding pads 9 and inner leads 7 with bonding wires 6.
As described above, probes have usually been put into contact with the bonding pads arranged along the four sides of the semiconductor integrated circuit device because the bonding pads are used for probing.
FIGS. 19 and 20 show how probe cards and their probes being in contact with bonding pads.
Shown in FIG. 19(a) are a semiconductor integrated circuit device 1 of which the bonding pads are arranged along its four sides and a probe card 19a in a common shape of which the probe needles 8 are arranged so as to be positioned along the four sides of the semiconductor integrated circuit device 1, to inspect it. The probe card 19a inspects one semiconductor integrated circuit device 1 at a time.
Shown in FIG. 19(b) are a semiconductor integrated circuit device 1 of which the bonding pads are arranged along its four sides and a probe card 19b in a special shape which inspects two semiconductor integrated circuit devices 1 at a time. Some probe needles 8 are slanted to access the bonding pads on some sides of the semiconductor integrated circuit device 1, accordingly the probe card 19b is difficult to make and costly.
Shown in FIG. 20(a) are four semiconductor integrated circuit devices 1 and a probe card 20a to inspect four devices 1 at a time. The bonding pads of each semiconductor integrated circuit device 1 are arranged along two opposite sides of the device 1 and the probe needles 8 of the probe card 20a are arranged in two rows.
Shown in FIG. 20(b) are eight semiconductor integrated circuit devices 1 (four devices/row×two rows) and a probe card 20b to inspect eight devices 1 at a time. The bonding pads of each semiconductor integrated circuit device 1 are arranged along two opposite sides of the device 1 and the probe needles 8 of the probe card 20b are arranged in four rows.
Shown in FIG. 20(c) are 16 semiconductor integrated circuit devices 1 (four devices/row×four rows) and a probe card 20c to inspect 16 devices 1 at a time. The bonding pads of each semiconductor integrated circuit device 1 are arranged along a side of the device 1 and the probes 8 of the probe card 20c are arranged in four rows.
Although the probe cards 20b and 20c have four rows of probes 8, they are relatively easy to make because no probes are slant.
As described above, it is important to make such probe cards for inspecting a plurality of semiconductor integrated circuit devices at a time easy to produce and inexpensive. For the purposes, it is desirable to arrange bonding pads along one side or two opposite sides rather than the four sides of each semiconductor integrated circuit device 1.
A semiconductor integrated circuit device with bonding pads along its two opposite sides is disclosed in JP-A-133338/1992.
As described above, semiconductor integrated circuit devices with bonding pads on their four sides have to be inspected one by one unless probe cards in special shapes as mentioned above are used. Every time one semiconductor integrated circuit device has been inspected, the probe card has to be shifted to the next device and its probes have to be put into contact with the bonding pads of the device; accordingly the inspection time per wafer is as long as the inspection time per semiconductor integrated circuit device multiplied by the number of devices on a wafer. Such a long inspection time directly affects the manufacturing cost of semiconductor integrated circuit devices. This cost-increasing factor can not be ignored in manufacturing inexpensive semiconductor integrated circuit devices in particular.
In accordance with the above, the object of the present invention is to provide an improved semiconductor integrated circuit device of which a plurality of units on a wafer to easily be inspected at a time so as to reduce the time and cost of the inspection.